msm8937.dtsi中
aliases { i2c1 = &i2c_1; i2c2 = &i2c_2; i2c3 = &i2c_3; i2c4 = &i2c_4; i2c5 = &i2c_5; i2c6 = &i2c_6; i2c8 = &i2c_8; };
i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */ compatible = “qcom,i2c-msm-v2”; #address-cells = <1>; #size-cells = <0>; reg-names = “qup_phys_addr”; reg = <0x78b5000 0x600>; interrupt-names = “qup_irq”; interrupts = <0 95 0>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = “iface_clk”, “core_clk”; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;
pinctrl-names = “i2c_active”, “i2c_sleep”; pinctrl-0 = <&i2c_1_active>; pinctrl-1 = <&i2c_1_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <86>; dmas = <&dma_blsp1 4 64 0x20000020 0x20>, <&dma_blsp1 5 32 0x20000020 0x20>; dma-names = “tx”, “rx”; };
i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */ compatible = “qcom,i2c-msm-v2”; #address-cells = <1>; #size-cells = <0>; reg-names = “qup_phys_addr”; reg = <0x78b6000 0x600>; interrupt-names = “qup_irq”; interrupts = <0 96 0>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = “iface_clk”, “core_clk”; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;
pinctrl-names = “i2c_active”, “i2c_sleep”; pinctrl-0 = <&i2c_2_active>; pinctrl-1 = <&i2c_2_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <86>; dmas = <&dma_blsp1 6 64 0x20000020 0x20>, <&dma_blsp1 7 32 0x20000020 0x20>; dma-names = “tx”, “rx”; };
i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */ compatible = “qcom,i2c-msm-v2”; #address-cells = <1>; #size-cells = <0>; reg-names = “qup_phys_addr”; reg = <0x78b7000 0x600>; interrupt-names = “qup_irq”; interrupts = <0 97 0>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = “iface_clk”, “core_clk”; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;
pinctrl-names = “i2c_active”, “i2c_sleep”; pinctrl-0 = <&i2c_3_active>; pinctrl-1 = <&i2c_3_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <86>; dmas = <&dma_blsp1 8 64 0x20000020 0x20>, <&dma_blsp1 9 32 0x20000020 0x20>; dma-names = “tx”, “rx”; };
i2c_4: i2c@78b8000 { /* BLSP1 QUP3 */ compatible = “qcom,i2c-msm-v2”; #address-cells = <1>; #size-cells = <0>; reg-names = “qup_phys_addr”; reg = <0x78b8000 0x600>; interrupt-names = “qup_irq”; interrupts = <0 98 0>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = “iface_clk”, “core_clk”; clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>, <&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>;
pinctrl-names = “i2c_active”, “i2c_sleep”; pinctrl-0 = <&i2c_4_active>; pinctrl-1 = <&i2c_4_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <86>; dmas = <&dma_blsp1 10 64 0x20000020 0x20>, <&dma_blsp1 11 32 0x20000020 0x20>; dma-names = “tx”, “rx”; };
i2c_5: i2c@7af5000 { // BLSP2 QUP1 compatible = “qcom,i2c-msm-v2”; #address-cells = <1>; #size-cells = <0>; reg-names = “qup_phys_addr”; reg = <0x7af5000 0x600>; interrupt-names = “qup_irq”; interrupts = <0 299 0>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = “iface_clk”, “core_clk”; clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, <&clock_gcc clk_gcc_blsp2_qup1_i2c_apps_clk>;
pinctrl-names = “i2c_active”, “i2c_sleep”; pinctrl-0 = <&i2c_5_active>; pinctrl-1 = <&i2c_5_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <84>; dmas = <&dma_blsp2 4 64 0x20000020 0x20>, <&dma_blsp2 5 32 0x20000020 0x20>; dma-names = “tx”, “rx”; };
i2c_6: i2c@7af6000 { compatible = “qcom,i2c-msm-v2”; #address-cells = <1>; #size-cells = <0>; reg-names = “qup_phys_addr”; reg = <0x7af6000 0x600>; interrupt-names = “qup_irq”; interrupts = <0 300 0>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = “iface_clk”, “core_clk”; clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, <&clock_gcc clk_gcc_blsp2_qup2_i2c_apps_clk>;
pinctrl-names = “i2c_active”, “i2c_sleep”; pinctrl-0 = <&i2c_6_active>; pinctrl-1 = <&i2c_6_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <84>; dmas = <&dma_blsp2 6 64 0x20000020 0x20>, <&dma_blsp2 7 32 0x20000020 0x20>; dma-names = “tx”, “rx”; };
i2c_8: i2c@7af8000 { // BLSP2 QUP4 compatible = “qcom,i2c-msm-v2”; #address-cells = <1>; #size-cells = <0>; reg-names = “qup_phys_addr”; reg = <0x7af8000 0x600>; interrupt-names = “qup_irq”; interrupts = <0 302 0>; qcom,clk-freq-out = <400000>; qcom,clk-freq-in = <19200000>; clock-names = “iface_clk”, “core_clk”; clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>, <&clock_gcc clk_gcc_blsp2_qup4_i2c_apps_clk>;
pinctrl-names = “i2c_active”, “i2c_sleep”; pinctrl-0 = <&i2c_8_active>; pinctrl-1 = <&i2c_8_sleep>; qcom,noise-rjct-scl = <0>; qcom,noise-rjct-sda = <0>; qcom,master-id = <84>; dmas = <&dma_blsp2 10 64 0x20000020 0x20>, <&dma_blsp2 11 32 0x20000020 0x20>; dma-names = “tx”, “rx”; };
msm8937-pinctrl.dtsi
i2c_1 { i2c_1_active: i2c_1_active { /* active state */ mux { pins = “gpio2”, “gpio3”; function = “blsp_i2c1”; };
config { pins = “gpio2”, “gpio3”; drive-strength = <2>; bias-disable; }; };
i2c_1_sleep: i2c_1_sleep { /* suspended state */ mux { pins = “gpio2”, “gpio3”; function = “gpio”; };
config { pins = “gpio2”, “gpio3”; drive-strength = <2>; bias-disable; }; }; };
i2c_2 { i2c_2_active: i2c_2_active { /* active state */ mux { pins = “gpio6”, “gpio7”; function = “blsp_i2c2”; };
config { pins = “gpio6”, “gpio7”; drive-strength = <2>; bias-disable; }; };
i2c_2_sleep: i2c_2_sleep { /* suspended state */ mux { pins = “gpio6”, “gpio7”; function = “gpio”; };
config { pins = “gpio6”, “gpio7”; drive-strength = <2>; bias-disable; }; }; };
i2c_3 { i2c_3_active: i2c_3_active { /* active state */ mux { pins = “gpio10”, “gpio11”; function = “blsp_i2c3”; };
config { pins = “gpio10”, “gpio11”; drive-strength = <2>; bias-disable; }; };
i2c_3_sleep: i2c_3_sleep { /* suspended state */ mux { pins = “gpio10”, “gpio11”; function = “gpio”; };
config { pins = “gpio10”, “gpio11”; drive-strength = <2>; bias-disable; }; }; };
i2c_4 { i2c_4_active: i2c_4_active { /* active state */ mux { pins = “gpio14”, “gpio15”; function = “blsp_i2c4”; };
config { pins = “gpio14”, “gpio15”; drive-strength = <2>; bias-disable; }; };
i2c_4_sleep: i2c_4_sleep { /* suspended state */ mux { pins = “gpio14”, “gpio15”; function = “gpio”; };
config { pins = “gpio14”, “gpio15”; drive-strength = <2>; bias-disable; }; }; };
i2c_5 { i2c_5_active: i2c_5_active { /* active state */ mux { pins = “gpio18”, “gpio19”; function = “blsp_i2c5”; };
config { pins = “gpio18”, “gpio19”; drive-strength = <2>; bias-disable; }; };
i2c_5_sleep: i2c_5_sleep { /* suspended state */ mux { pins = “gpio18”, “gpio19”; function = “gpio”; };
config { pins = “gpio18”, “gpio19”; drive-strength = <2>; bias-disable; }; }; };
i2c_6 { i2c_6_active: i2c_6_active { /* active state */ mux { pins = “gpio22”, “gpio23”; function = “blsp_i2c6”; };
config { pins = “gpio22”, “gpio23”; drive-strength = <2>; bias-disable; }; };
i2c_6_sleep: i2c_6_sleep { /* suspended state */ mux { pins = “gpio22”, “gpio23”; function = “gpio”; };
config { pins = “gpio22”, “gpio23”; drive-strength = <2>; bias-disable; }; }; };
i2c_8 { i2c_8_active: i2c_8_active { /* active state */ mux { pins = “gpio98”, “gpio99”; function = “blsp_i2c8”; };
config { pins = “gpio98”, “gpio99”; drive-strength = <2>; bias-disable; }; };
i2c_8_sleep: i2c_8_sleep { /* suspended state */ mux { pins = “gpio98”, “gpio99”; function = “gpio”; };
config { pins = “gpio98”, “gpio99”; drive-strength = <2>; bias-disable; }; }; };
版权声明：本文内容由互联网用户自发贡献，该文观点仅代表作者本人。本站仅提供信息存储空间服务，不拥有所有权，不承担相关法律责任。如发现本站有涉嫌侵权/违法违规的内容， 请发送邮件至 举报，一经查实，本站将立刻删除。
发布者：全栈程序员栈长，转载请注明出处：https://javaforall.cn/180479.html原文链接：https://javaforall.cn
