JEDEC 发布了 LPDDR5 内存标准 JESD209-5B 的新修订版，按照这份新的标准，除了在性能和功率作了改进以外，还对 LPDDR5 进行了扩展，提出了名为 LPDDR5X 的内存扩展规格。 LPDDR5X传输速度可高达 8533MT/s（或者说等效 8533MHz），预期 LPDDR5 和 LPDDR5X 将同时在市场上推出，互为补充。
两种内存颗粒的引脚完全兼容，这意味着支持新内存的处理器在内存控制上得以大为简化。
为了提高数据传输速率以及提高低功耗内存子系统的可靠性，LPDDR5X 引入了名为 pre-emphasis（预加重）的功能来提高信噪比（从而达成更高的频率和性能）并降低误码率以及自适应刷新管理，此外还有每引脚决策反馈均衡器，可以增强内存通道稳健性。
和 LPDDR5 的 6400MT/s 相比，LPDDR5X 的 8533MT/s 在理论性能上提升了 33%，这对于人工智能、深度学习等应用来说都可能得以受益，尤其是如果 PC 处理器也提供相应支持的话，将获得 DDR5 也无法提供了的庞大内存带宽，核显将显著受益。
目前三星和镁光已经确认会支持 LPDDR5X，Synopsys 将提供相关内存的 IP，至此，内存厂商和设计厂商都已经基本就绪。
JEDEC and the JC-42.6 Subcommittee for Low Power Memories has announced the publication of the new JESD209-5B standard which now includes improvements to LPDDR5, as well as an extension for the standard in the form of new LPDDR5X.
The new LPDDR5X standard is an evolutionary step over LPDDR5, further increasing the data rates possible by 33% from 6400Mbps to 8533Mbps.
The industry had first shifted over to the LPDDR5 memory standard back in 2020, with the first generation SoCs and memory modules running at a speed of 5500Mbps which had gotten an upgrade to 6400Mbps speeds in recent 2021 flagship devices.
As IP vendors and DRAM manufacturers have matured their LPDDR5 products, there’s an increasing need to look for further updates to the LPDDR5 standard as we’ve essentially reached the maximum data rates of the standard in current generation implementations.
While we currently don’t have access to the official documentation to detail the exact changes, back in February Cadence had written more extensively about the new improvements in LP5X over LP5:
To Improve READ SI performance in the dual rank system at high speeds that Lpddr5X devices support a Unified NT-ODT Behavior has been defined. Unified NT-ODT is a requirement for all LPDDR5X devices
To support high data rates for Lpddr5X, we need a way to compensate for transmission loss. This has been achieved by defining the pre-emphasis function. Lpddr5X devices have pull up or down pre-emphasis for each of the lower/upper byte lane programming.
Rx Offset Calibration Training - LPDDR5X SDRAM provides Offset Calibration Training for adjusting DQ Rx offset and Offset Calibration Training is recommended for every power-up and initialization training sequence to cope with the SDRAM operating condition change
Extended Latencies - LPDDR5X SDRAM devices support extended Read, Write, nWR, ODTLon and ODTLoff Latency Values to account for longer number of cycle it takes to do the data access to memory array. WCK2CK Sync AC Parameters are also extended.
LPDDR5X SDRAM Devices support Per-pin controlled Decision Feedback Equalization: DFE. This includes new Mode Registers 70/71/72/73/74.
New LPDDR5X SDRAM Device specific Clock AC Timings for 937.5/1066.5MHz and Write Clock AC Timings for 3750/4266.5MHz.
New Mode register fields or additional conditions on the use of existing fields have been added to several Mode registers for LPDDR5X devices. Some of the examples of changed MR are MR0, MR1, MR2, MR13, MR15, MR41, MR58, MR69, etc.
LPDDR5X SDRAM devices do not support 8 Bank Mode of operations. 8 Bank Mode doesn’t offer the architectural benefit of more bank interleaving resources and core operation timings at high speed that 16B and BG Mode have. It is specially limiting for high speed LPDDR5X devices support leading JEDEC to drop 8 Bank Mode support for LPDDR5X.
In short, the new standard covers deeper tweaks to the architecture and operating mode of the memory standard to achieve higher data-rates.
For eventual mobile SoCs using 8533Mbps memory, the peak theoretical available bandwidth would grow from 51.2GB/s to 68.26GB/s, allowing future designs to further increase CPU and GPU performances. It’s to be noted, that we haven’t heard much about power efficiency improvements of the new LP5X standard, so I assume that we’ll be relying on DRAM vendors to improve power efficiency via more advanced manufacturing nodes to keep total power usage inside of devices in check.
we’ll be seeing LPDDR5X in future late 2022 or 2023 SoCs.
