目录
- 介绍
- 升级Vivado工程脚本
- 准备Vivado
- 修改版本
- 修改器件和单板
- 查找器件
- 查找单板
- 升级IP
- 注意事项
- 定制工程名称
- 命令执行记录
介绍
Vivado可以导出脚本，保存创建工程的相关命令和配置，并可以在需要的时候使用脚本重建Vivado工程。脚本通常只有KB级别大小，远远小于工程打包文件的大小，因此便于备份和版本管理。 脚本里指定了Vivado的版本、器件的型号，IP的版本。如果导出脚本时的相关版本，和恢复工程时的相关版本不一样，会导致创建工程失败。可以通过手工检查和修改相关版本信息，升级Vivado工程脚本，使新的Vivado也能恢复出对应的工程。 目前我电脑中只有Vivado 2020.2。但是得到了一份Vivado 2020.1为开发板vck190 es的创建的工程脚本。下面以把前述脚本升级到Vivado 2020.2为例，讨论如何升级Vivado工程脚本。
升级Vivado工程脚本
准备Vivado
首先启动Vivado 2020.2，在TCL console窗口进入工程脚本所在的目录，使用命令“source”执行对应的脚本。 注意，Vivado遵循Unix/Linux习惯，使用“/”作为目录分隔符。对于目录“C:UsershankfDownloads3-VitisEmbdPfm-Versal-lab.tarref_files_v202step1_vivado”，要改成“C:/Users/hankf/Downloads/3-VitisEmbdPfm-Versal-lab.tar/ref_files_v202/step1_vivado”。否则，Vivado会报告错误“couldn't change working directory”。
修改版本
Vivado工程脚本里含有版本信息，对应的TCL代码是“set scripts_vivado_version 2020.1”。如果使用Vivado 2020.2，需要将其中的2020.1改为2020.2。
代码语言：javascript复制set scripts_vivado_version 2020.2修改器件和单板
Vivado工程脚本里也指定了器件和单板信息。vck190 es使用的是ES器件，Vivado 2020.2没有使能ES器件和包含vck190 es单板的信息。如果执行上述，会报告错误“ERROR: [Coretcl 2-106] Specified part could not be found.”。
原始的器件和单板信息：
代码语言：javascript复制 create_project project_1 myproj -part xcvc1902-vsva2197-2MP-e-S-es1
set_property BOARD_PART xilinx.com:vck190_es:part0:1.0 [current_project]Vivado 2020.2默认支持器件vc1902、包含量产单板vck190的单板信息。因此需要把Vivado工程脚本里的器件和单板改为支持的型号。
修改后的器件和单板信息：
代码语言：javascript复制 create_project project_1 myproj -part xcvc1902-vsva2197-2MP-e-S
set_property BOARD_PART xilinx.com:vck190:part0:2.0 [current_project]如果不知道对应的器件和单板，可以使用get_parts命令和get_boards命令，查找Vivado支持的器件和单板。
查找器件
使用get_parts命令，列出Vivado支持的器件。Vivado支持的器件型号太多，导致它只显示一部分。最好使用通配符，只显示我们感兴趣的器件型号。使用命令“get_parts vc1902”，只会显示出vc1902的相关型号，包括所有封装。如果指定更多的信息，会得到更少也更准确的器件。
代码语言：javascript复制get_parts *vc1902*
xcvc1902-viva1596-1LHP-i-L xcvc1902-viva1596-1LHP-i-S xcvc1902-viva1596-1LP-e-S xcvc1902-viva1596-1LP-i-L xcvc1902-viva1596-1LP-i-S xcvc1902-viva1596-1MP-e-S xcvc1902-viva1596-1MP-i-L xcvc1902-viva1596-1MP-i-S xcvc1902-viva1596-2HP-i-S xcvc1902-viva1596-2LP-e-L xcvc1902-viva1596-2LP-e-S xcvc1902-viva1596-2MP-e-L xcvc1902-viva1596-2MP-e-S xcvc1902-viva1596-2MP-i-L xcvc1902-viva1596-2MP-i-S xcvc1902-viva1596-3HP-e-S xcvc1902-vsva2197-1LHP-i-L xcvc1902-vsva2197-1LHP-i-S xcvc1902-vsva2197-1LP-e-S xcvc1902-vsva2197-1LP-i-L xcvc1902-vsva2197-1LP-i-S xcvc1902-vsva2197-1MP-e-S xcvc1902-vsva2197-1MP-i-L xcvc1902-vsva2197-1MP-i-S xcvc1902-vsva2197-2HP-i-S xcvc1902-vsva2197-2LP-e-L xcvc1902-vsva2197-2LP-e-S xcvc1902-vsva2197-2MP-e-L xcvc1902-vsva2197-2MP-e-S xcvc1902-vsva2197-2MP-i-L xcvc1902-vsva2197-2MP-i-S xcvc1902-vsva2197-3HP-e-S xcvc1902-vsvd1760-1LHP-i-L xcvc1902-vsvd1760-1LHP-i-S xcvc1902-vsvd1760-1LP-e-S xcvc1902-vsvd1760-1LP-i-L xcvc1902-vsvd1760-1LP-i-S xcvc1902-vsvd1760-1MP-e-S xcvc1902-vsvd1760-1MP-i-L xcvc1902-vsvd1760-1MP-i-S xcvc1902-vsvd1760-2HP-i-S xcvc1902-vsvd1760-2LP-e-L xcvc1902-vsvd1760-2LP-e-S xcvc1902-vsvd1760-2MP-e-L xcvc1902-vsvd1760-2MP-e-S xcvc1902-vsvd1760-2MP-i-L xcvc1902-vsvd1760-2MP-i-S xcvc1902-vsvd1760-3HP-e-S
get_parts *xcvc1902-vsva2197-2MP*
xcvc1902-vsva2197-2MP-e-L xcvc1902-vsva2197-2MP-e-S xcvc1902-vsva2197-2MP-i-L xcvc1902-vsva2197-2MP-i-S查找单板
使用get_boards命令，列出Vivado支持的单板。Vivado支持的单板型号也很多。最好使用通配符，只显示我们感兴趣的单板型号。使用命令“get_boards vck”，只会显示出vck190。
代码语言：javascript复制get_boards *vck*
get_boards: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1118.992 ; gain = 0.000
xilinx.com:vck190:2.0升级IP
Vivado版本变化时，IP也可能变化。执行前述脚本创建工程，会得到下列错误。
代码语言：javascript复制WARNING: [IP_Flow 19-2162] IP 'design_1_ai_engine_0_0' is locked:
* IP definition 'AI Engine (1.0)' for IP 'design_1_ai_engine_0_0' (customized with software release 2020.2) has a newer major version in the IP Catalog.
ERROR: [BD 41-542] Parameter cannot be set on a locked block. The block 'ai_engine_0' is locked, because: * IP definition 'AI Engine (1.0)' for IP 'design_1_ai_engine_0_0' (customized with software release 2020.2) has a newer major version in the IP Catalog. 可以使用get_ipdefs命令，得到详细的IP信息。执行命令“get_ipdefs engine”，检查Vivado 2020.2里的ai_engine信息，发现新的版本是2.0。
代码语言：javascript复制get_ipdefs *engine*
xilinx.com:ip:ai_engine:2.0在Vivado 2020.1的工程脚本里，还是使用的ai_engine 1.0。
代码语言：javascript复制set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "
xilinx.com:ip:ai_engine:1.0
xilinx.com:ip:axi_intc:4.1
xilinx.com:ip:smartconnect:1.0
xilinx.com:ip:clk_wizard:1.0
xilinx.com:ip:axi_noc:1.0
xilinx.com:ip:proc_sys_reset:5.0
xilinx.com:ip:versal_cips:2.1
"
set ai_engine_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ai_engine:1.0 ai_engine_0 ]把使用的ai_engine的版本，从1.0改为2.0。
代码语言：javascript复制set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "
xilinx.com:ip:ai_engine:2.0
xilinx.com:ip:axi_intc:4.1
xilinx.com:ip:smartconnect:1.0
xilinx.com:ip:clk_wizard:1.0
xilinx.com:ip:axi_noc:1.0
xilinx.com:ip:proc_sys_reset:5.0
xilinx.com:ip:versal_cips:2.1
"
set ai_engine_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ai_engine:2.0 ai_engine_0 ]关闭Vivado工程，再删除对应目录，重新执行“source system_step1.tcl”，可以成功创建工程。
注意事项
如果IP变化比较大，比如接口有变化，仅仅升级IP版本，也不能创建出正确的工程。这时请根据IP的文档，重新定制IP，和连接IP相关的接口。
定制工程名称
Vivado脚本里的命令create_project也指定了工程名称，默认是“project_1”。如果想使用其它工程名，把“project_1”改为你需要的工程名。 Vivado脚本会在当前目录下，创建一个子目录。Vivado脚本里的命令create_project也指定了子目录名，默认是“myproj”。如果想使用其它目录名，把“myproj”改为你需要的目录名。
代码语言：javascript复制if { $list_projs eq "" } {
create_project project_1 myproj -part xcvc1902-vsva2197-2MP-e-S
set_property BOARD_PART xilinx.com:vck190:part0:2.0 [current_project]
}命令执行记录
下面是更详细的命令执行记录。
代码语言：javascript复制cd C:UsershankfDownloads3-VitisEmbdPfm-Versal-lab.tarref_files_v202step1_vivado
couldn't change working directory to "C:UsershankfDownloads-VitisEmbdPfm-Versal-lab.tar
ef_files_v202step1_vivado": no such file or directory
cd C:/Users/hankf/Downloads/3-VitisEmbdPfm-Versal-lab.tar/ref_files_v202/step1_vivado
dir
WARNING: [Common 17-259] Unknown Tcl command 'dir' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell.
Volume in drive C is OSDisk
Volume Serial Number is BA3F-7D4D
Directory of C:UsershankfDownloads3-VitisEmbdPfm-Versal-lab.tarref_files_v202step1_vivado
2021/02/23 10:32 <DIR> .
2021/02/23 10:32 <DIR> ..
2021/02/22 12:09 109 debug.log
2020/11/26 01:14 2,212 export_xsa.tcl
2020/11/26 01:14 960 Makefile
2021/02/22 14:14 <DIR> myproj
2021/02/22 12:16 26,449 system_step1.tcl
2021/02/23 09:25 33,481 vivado_boards.txt
7 File(s) 124,428 bytes
3 Dir(s) 23,547,252,736 bytes free
source system_step1.tcl
# namespace eval _tcl {
# proc get_script_folder {} {
# set script_path [file normalize [info script]]
# set script_folder [file dirname $script_path]
# return $script_folder
# }
# }
# variable script_folder
# set script_folder [_tcl::get_script_folder]
# set scripts_vivado_version 2020.1
# set current_vivado_version [version -short]
# if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
# puts ""
# catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script."}
#
# return 1
# }
ERROR: [BD::TCL 103-2041] This script was generated using Vivado <2020.1> and is being run in <2020.2> of Vivado. Please run the script in Vivado <2020.1> then open the design in Vivado <2020.2>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script.
1
get_parts *vc1902*
xcvc1902-viva1596-1LHP-i-L xcvc1902-viva1596-1LHP-i-S xcvc1902-viva1596-1LP-e-S xcvc1902-viva1596-1LP-i-L xcvc1902-viva1596-1LP-i-S xcvc1902-viva1596-1MP-e-S xcvc1902-viva1596-1MP-i-L xcvc1902-viva1596-1MP-i-S xcvc1902-viva1596-2HP-i-S xcvc1902-viva1596-2LP-e-L xcvc1902-viva1596-2LP-e-S xcvc1902-viva1596-2MP-e-L xcvc1902-viva1596-2MP-e-S xcvc1902-viva1596-2MP-i-L xcvc1902-viva1596-2MP-i-S xcvc1902-viva1596-3HP-e-S xcvc1902-vsva2197-1LHP-i-L xcvc1902-vsva2197-1LHP-i-S xcvc1902-vsva2197-1LP-e-S xcvc1902-vsva2197-1LP-i-L xcvc1902-vsva2197-1LP-i-S xcvc1902-vsva2197-1MP-e-S xcvc1902-vsva2197-1MP-i-L xcvc1902-vsva2197-1MP-i-S xcvc1902-vsva2197-2HP-i-S xcvc1902-vsva2197-2LP-e-L xcvc1902-vsva2197-2LP-e-S xcvc1902-vsva2197-2MP-e-L xcvc1902-vsva2197-2MP-e-S xcvc1902-vsva2197-2MP-i-L xcvc1902-vsva2197-2MP-i-S xcvc1902-vsva2197-3HP-e-S xcvc1902-vsvd1760-1LHP-i-L xcvc1902-vsvd1760-1LHP-i-S xcvc1902-vsvd1760-1LP-e-S xcvc1902-vsvd1760-1LP-i-L xcvc1902-vsvd1760-1LP-i-S xcvc1902-vsvd1760-1MP-e-S xcvc1902-vsvd1760-1MP-i-L xcvc1902-vsvd1760-1MP-i-S xcvc1902-vsvd1760-2HP-i-S xcvc1902-vsvd1760-2LP-e-L xcvc1902-vsvd1760-2LP-e-S xcvc1902-vsvd1760-2MP-e-L xcvc1902-vsvd1760-2MP-e-S xcvc1902-vsvd1760-2MP-i-L xcvc1902-vsvd1760-2MP-i-S xcvc1902-vsvd1760-3HP-e-S
get_boards *vck*
get_boards: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1118.992 ; gain = 0.000
xilinx.com:vck190:2.0
source system_step1.tcl
# namespace eval _tcl {
# proc get_script_folder {} {
# set script_path [file normalize [info script]]
# set script_folder [file dirname $script_path]
# return $script_folder
# }
# }
# variable script_folder
# set script_folder [_tcl::get_script_folder]
# set scripts_vivado_version 2020.2
# set current_vivado_version [version -short]
# if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
# puts ""
# catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script."}
#
# return 1
# }
# set list_projs [get_projects -quiet]
# if { $list_projs eq "" } {
# create_project project_1 myproj -part xcvc1902-vsva2197-2MP-e-S
# set_property BOARD_PART xilinx.com:vck190:part0:2.0 [current_project]
# }
INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
Current project path is 'C:/Users/hankf/Downloads/3-VitisEmbdPfm-Versal-lab.tar/ref_files_v202/step1_vivado/myproj'
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2020.2/data/ip'.
create_project: Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 1118.992 ; gain = 0.000
# variable design_name
# set design_name design_1
# set errMsg ""
# set nRet 0
# set cur_design [current_bd_design -quiet]
# set list_cells [get_bd_cells -quiet]
# if { ${design_name} eq "" } {
# # USE CASES:
# # 1) Design_name not set
#
# set errMsg "Please set the variable <design_name> to a non-empty value."
# set nRet 1
#
# } elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# # USE CASES:
# # 2): Current design opened AND is empty AND names same.
# # 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# # 4): Current design opened AND is empty AND names diff; design_name exists in project.
#
# if { $cur_design ne $design_name } {
# common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
# set design_name [get_property NAME $cur_design]
# }
# common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
#
# } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# # USE CASES:
# # 5) Current design opened AND has components AND same names.
#
# set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
# set nRet 1
# } elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# # USE CASES:
# # 6) Current opened design, has components, but diff names, design_name exists in project.
# # 7) No opened design, design_name exists in project.
#
# set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
# set nRet 2
#
# } else {
# # USE CASES:
# # 8) No opened design, design_name not in project.
# # 9) Current opened design, has components, but diff names, design_name not in project.
#
# common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
#
# create_bd_design $design_name
#
# common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
# current_bd_design $design_name
#
# }
INFO: [BD::TCL 103-2003] Currently there is no design <design_1> in project, so creating one...
Wrote : <C:UsershankfDownloads3-VitisEmbdPfm-Versal-lab.tarref_files_v202step1_vivadomyprojproject_1.srcssources_1bddesign_1design_1.bd>
create_bd_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1144.547 ; gain = 25.555
INFO: [BD::TCL 103-2004] Making design <design_1> as current_bd_design.
# common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to "$design_name"."
INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "design_1".
# if { $nRet != 0 } {
# catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
# return $nRet
# }
# set bCheckIPsPassed 1
# set bCheckIPs 1
# if { $bCheckIPs == 1 } {
# set list_check_ips "
# xilinx.com:ip:ai_engine:1.0
# xilinx.com:ip:axi_intc:4.1
# xilinx.com:ip:smartconnect:1.0
# xilinx.com:ip:clk_wizard:1.0
# xilinx.com:ip:axi_noc:1.0
# xilinx.com:ip:proc_sys_reset:5.0
# xilinx.com:ip:versal_cips:2.1
# "
#
# set list_ips_missing ""
# common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
#
# foreach ip_vlnv $list_check_ips {
# set ip_obj [get_ipdefs -all $ip_vlnv]
# if { $ip_obj eq "" } {
# lappend list_ips_missing $ip_vlnv
# }
# }
#
# if { $list_ips_missing ne "" } {
# catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:n $list_ips_missingnnResolution: Please add the repository containing the IP(s) to the project." }
# set bCheckIPsPassed 0
# }
#
# }
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
xilinx.com:ip:ai_engine:1.0 xilinx.com:ip:axi_intc:4.1 xilinx.com:ip:smartconnect:1.0 xilinx.com:ip:clk_wizard:1.0 xilinx.com:ip:axi_noc:1.0 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:versal_cips:2.1 .
# if { $bCheckIPsPassed != 1 } {
# common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
# return 3
# }
# proc create_root_design { parentCell } {
#
# variable script_folder
# variable design_name
#
# if { $parentCell eq "" } {
# set parentCell [get_bd_cells /]
# }
#
# # Get object for parentCell
# set parentObj [get_bd_cells $parentCell]
# if { $parentObj == "" } {
# catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
# return
# }
#
# # Make sure parentObj is hier blk
# set parentType [get_property TYPE $parentObj]
# if { $parentType ne "hier" } {
# catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
# return
# }
#
# # Save current instance; Restore later
# set oldCurInst [current_bd_instance .]
#
# # Set parent object as current
# current_bd_instance $parentObj
#
#
# # Create interface ports
# set ddr4_dimm1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_dimm1 ]
#
# set ddr4_dimm1_sma_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ddr4_dimm1_sma_clk ]
# set_property -dict [ list
# CONFIG.FREQ_HZ {200000000}
# ] $ddr4_dimm1_sma_clk
#
#
# # Create ports
#
# # Create instance: ai_engine_0, and set properties
# set ai_engine_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ai_engine:1.0 ai_engine_0 ]
# set_property -dict [ list
# CONFIG.CLK_NAMES {}
# CONFIG.FIFO_TYPE_MI_AXIS {}
# CONFIG.FIFO_TYPE_SI_AXIS {}
# CONFIG.NAME_MI_AXIS {}
# CONFIG.NAME_SI_AXIS {}
# CONFIG.NUM_CLKS {0}
# CONFIG.NUM_MI_AXI {0}
# CONFIG.NUM_MI_AXIS {0}
# CONFIG.NUM_SI_AXIS {0}
# ] $ai_engine_0
#
# set_property -dict [ list
# CONFIG.CATEGORY {NOC}
# ] [get_bd_intf_pins /ai_engine_0/S00_AXI]
#
# # Create instance: axi_intc_0, and set properties
# set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ]
# set_property -dict [ list
# CONFIG.C_IRQ_CONNECTION {1}
# ] $axi_intc_0
#
# # Create instance: axi_smc, and set properties
# set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
# set_property -dict [ list
# CONFIG.NUM_SI {1}
# ] $axi_smc
#
# # Create instance: clk_wizard_0, and set properties
# set clk_wizard_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard:1.0 clk_wizard_0 ]
# set_property -dict [ list
# CONFIG.CLKFBOUT_MULT {28.000000}
# CONFIG.CLKOUT1_DIVIDE {28.000000}
# CONFIG.CLKOUT2_DIVIDE {14.000000}
# CONFIG.CLKOUT3_DIVIDE {7.000000}
# CONFIG.CLKOUT_DRIVES {BUFG,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG}
# CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None}
# CONFIG.CLKOUT_GROUPING {Auto,Auto,Auto,Auto,Auto,Auto,Auto}
# CONFIG.CLKOUT_MATCHED_ROUTING {false,false,false,false,false,false,false}
# CONFIG.CLKOUT_PORT {clk_out1,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7}
# CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE {50.000,50.000,50.000,50.000,50.000,50.000,50.000}
# CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY {100.000,200.000,400.000,100.000,100.000,100.000,100.000}
# CONFIG.CLKOUT_REQUESTED_PHASE {0.000,0.000,0.000,0.000,0.000,0.000,0.000}
# CONFIG.CLKOUT_USED {true,true,true,false,false,false,false}
# CONFIG.USE_LOCKED {true}
# ] $clk_wizard_0
#
# # Create instance: pl_noc, and set properties
# set pl_noc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.0 pl_noc ]
# set_property -dict [ list
# CONFIG.NUM_CLKS {0}
# CONFIG.NUM_MI {0}
# CONFIG.NUM_NMI {1}
# CONFIG.NUM_SI {0}
# ] $pl_noc
#
# set_property -dict [ list
# CONFIG.INI_STRATEGY {load}
# ] [get_bd_intf_pins /pl_noc/M00_INI]
#
# # Create instance: proc_sys_reset_1, and set properties
# set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ]
#
# # Create instance: proc_sys_reset_2, and set properties
# set proc_sys_reset_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_2 ]
#
# # Create instance: proc_sys_reset_3, and set properties
# set proc_sys_reset_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_3 ]
#
# # Create instance: ps_noc, and set properties
# set ps_noc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_noc:1.0 ps_noc ]
# set_property -dict [ list
# CONFIG.CH0_DDR4_0_BOARD_INTERFACE {ddr4_dimm1}
# CONFIG.CONTROLLERTYPE {DDR4_SDRAM}
# CONFIG.MC_COMPONENT_WIDTH {x8}
# CONFIG.MC_DATAWIDTH {64}
# CONFIG.MC_INPUTCLK0_PERIOD {5000}
# CONFIG.MC_INTERLEAVE_SIZE {128}
# CONFIG.MC_MEMORY_DEVICETYPE {UDIMMs}
# CONFIG.MC_MEMORY_SPEEDGRADE {DDR4-3200AA(22-22-22)}
# CONFIG.MC_NO_CHANNELS {Single}
# CONFIG.MC_RANK {1}
# CONFIG.MC_ROWADDRESSWIDTH {16}
# CONFIG.MC_STACKHEIGHT {1}
# CONFIG.MC_SYSTEM_CLOCK {Differential}
# CONFIG.NUM_CLKS {7}
# CONFIG.NUM_MC {1}
# CONFIG.NUM_MI {1}
# CONFIG.NUM_NSI {1}
# CONFIG.NUM_SI {6}
# CONFIG.sys_clk0_BOARD_INTERFACE {ddr4_dimm1_sma_clk}
# ] $ps_noc
#
# set_property -dict [ list
# CONFIG.DATA_WIDTH {128}
# CONFIG.REGION {0}
# CONFIG.CATEGORY {aie}
# ] [get_bd_intf_pins /ps_noc/M00_AXI]
#
# set_property -dict [ list
# CONFIG.DATA_WIDTH {128}
# CONFIG.REGION {0}
# CONFIG.CONNECTIONS {MC_0 { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} M00_AXI { read_bw {5} write_bw {5}} }
# CONFIG.DEST_IDS {M00_AXI:0x0}
# CONFIG.CATEGORY {ps_pmc}
# ] [get_bd_intf_pins /ps_noc/S00_AXI]
#
# set_property -dict [ list
# CONFIG.CONNECTIONS {MC_0 { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} }
# ] [get_bd_intf_pins /ps_noc/S00_INI]
#
# set_property -dict [ list
# CONFIG.DATA_WIDTH {128}
# CONFIG.REGION {0}
# CONFIG.CONNECTIONS {MC_0 { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} }
# CONFIG.CATEGORY {ps_rpu}
# ] [get_bd_intf_pins /ps_noc/S01_AXI]
#
# set_property -dict [ list
# CONFIG.DATA_WIDTH {128}
# CONFIG.REGION {0}
# CONFIG.CONNECTIONS {MC_0 { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} M00_AXI { read_bw {5} write_bw {5}} }
# CONFIG.DEST_IDS {M00_AXI:0x0}
# CONFIG.CATEGORY {ps_cci}
# ] [get_bd_intf_pins /ps_noc/S02_AXI]
#
# set_property -dict [ list
# CONFIG.DATA_WIDTH {128}
# CONFIG.REGION {0}
# CONFIG.CONNECTIONS {MC_0 { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} M00_AXI { read_bw {5} write_bw {5}} }
# CONFIG.DEST_IDS {M00_AXI:0x0}
# CONFIG.CATEGORY {ps_cci}
# ] [get_bd_intf_pins /ps_noc/S03_AXI]
#
# set_property -dict [ list
# CONFIG.DATA_WIDTH {128}
# CONFIG.REGION {0}
# CONFIG.CONNECTIONS {MC_0 { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} M00_AXI { read_bw {5} write_bw {5}} }
# CONFIG.DEST_IDS {M00_AXI:0x0}
# CONFIG.CATEGORY {ps_cci}
# ] [get_bd_intf_pins /ps_noc/S04_AXI]
#
# set_property -dict [ list
# CONFIG.DATA_WIDTH {128}
# CONFIG.REGION {0}
# CONFIG.CONNECTIONS {MC_0 { read_bw {5} write_bw {5} read_avg_burst {4} write_avg_burst {4}} M00_AXI { read_bw {5} write_bw {5}} }
# CONFIG.DEST_IDS {M00_AXI:0x0}
# CONFIG.CATEGORY {ps_cci}
# ] [get_bd_intf_pins /ps_noc/S05_AXI]
#
# set_property -dict [ list
# CONFIG.ASSOCIATED_BUSIF {S00_AXI}
# ] [get_bd_pins /ps_noc/aclk0]
#
# set_property -dict [ list
# CONFIG.ASSOCIATED_BUSIF {S01_AXI}
# ] [get_bd_pins /ps_noc/aclk1]
#
# set_property -dict [ list
# CONFIG.ASSOCIATED_BUSIF {S02_AXI}
# ] [get_bd_pins /ps_noc/aclk2]
#
# set_property -dict [ list
# CONFIG.ASSOCIATED_BUSIF {S03_AXI}
# ] [get_bd_pins /ps_noc/aclk3]
#
# set_property -dict [ list
# CONFIG.ASSOCIATED_BUSIF {S04_AXI}
# ] [get_bd_pins /ps_noc/aclk4]
#
# set_property -dict [ list
# CONFIG.ASSOCIATED_BUSIF {S05_AXI}
# ] [get_bd_pins /ps_noc/aclk5]
#
# set_property -dict [ list
# CONFIG.ASSOCIATED_BUSIF {M00_AXI}
# ] [get_bd_pins /ps_noc/aclk6]
#
# # Create instance: versal_cips_0, and set properties
# set versal_cips_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:versal_cips:2.1 versal_cips_0 ]
# set_property -dict [ list
# CONFIG.PMC_CRP_PL0_REF_CTRL_FREQMHZ {100}
# CONFIG.PMC_GPIO0_MIO_PERIPHERAL_ENABLE {1}
# CONFIG.PMC_GPIO1_MIO_PERIPHERAL_ENABLE {1}
# CONFIG.PMC_I2CPMC_PERIPHERAL_ENABLE {1}
# CONFIG.PMC_I2CPMC_PERIPHERAL_IO {PMC_MIO 46 .. 47}
# CONFIG.PMC_MIO_37_DIRECTION {out}
# CONFIG.PMC_MIO_37_OUTPUT_DATA {high}
# CONFIG.PMC_MIO_37_USAGE {GPIO}
# CONFIG.PMC_OSPI_PERIPHERAL_ENABLE {0}
# CONFIG.PMC_QSPI_GRP_FBCLK_ENABLE {1}
# CONFIG.PMC_QSPI_PERIPHERAL_DATA_MODE {x4}
# CONFIG.PMC_QSPI_PERIPHERAL_ENABLE {1}
# CONFIG.PMC_QSPI_PERIPHERAL_MODE {Dual Parallel}
# CONFIG.PMC_SD1_GRP_CD_ENABLE {1}
# CONFIG.PMC_SD1_GRP_POW_ENABLE {0}
# CONFIG.PMC_SD1_GRP_WP_ENABLE {0}
# CONFIG.PMC_SD1_PERIPHERAL_ENABLE {1}
# CONFIG.PMC_SD1_PERIPHERAL_IO {PMC_MIO 26 .. 36}
# CONFIG.PMC_SD1_SLOT_TYPE {SD 3.0}
# CONFIG.PMC_USE_PMC_NOC_AXI0 {1}
# CONFIG.PS_CAN1_PERIPHERAL_ENABLE {1}
# CONFIG.PS_CAN1_PERIPHERAL_IO {PMC_MIO 40 .. 41}
# CONFIG.PS_ENET0_GRP_MDIO_ENABLE {1}
# CONFIG.PS_ENET0_GRP_MDIO_IO {PS_MIO 24 .. 25}
# CONFIG.PS_ENET0_PERIPHERAL_ENABLE {1}
# CONFIG.PS_ENET0_PERIPHERAL_IO {PS_MIO 0 .. 11}
# CONFIG.PS_ENET1_PERIPHERAL_ENABLE {1}
# CONFIG.PS_ENET1_PERIPHERAL_IO {PS_MIO 12 .. 23}
# CONFIG.PS_GEN_IPI_0_ENABLE {1}
# CONFIG.PS_GEN_IPI_1_ENABLE {1}
# CONFIG.PS_GEN_IPI_2_ENABLE {1}
# CONFIG.PS_GEN_IPI_3_ENABLE {1}
# CONFIG.PS_GEN_IPI_4_ENABLE {1}
# CONFIG.PS_GEN_IPI_5_ENABLE {1}
# CONFIG.PS_GEN_IPI_6_ENABLE {1}
# CONFIG.PS_GEN_IPI_PMCNOBUF_ENABLE {1}
# CONFIG.PS_GEN_IPI_PMC_ENABLE {1}
# CONFIG.PS_GEN_IPI_PSM_ENABLE {1}
# CONFIG.PS_GPIO2_MIO_PERIPHERAL_ENABLE {0}
# CONFIG.PS_I2C1_PERIPHERAL_ENABLE {1}
# CONFIG.PS_I2C1_PERIPHERAL_IO {PMC_MIO 44 .. 45}
# CONFIG.PS_M_AXI_GP2_DATA_WIDTH {128}
# CONFIG.PS_NUM_FABRIC_RESETS {1}
# CONFIG.PS_PCIE_RESET_ENABLE {1}
# CONFIG.PS_PCIE_RESET_IO {PS_MIO 18 .. 19}
# CONFIG.PS_TTC0_PERIPHERAL_ENABLE {1}
# CONFIG.PS_TTC3_PERIPHERAL_ENABLE {0}
# CONFIG.PS_UART0_PERIPHERAL_ENABLE {1}
# CONFIG.PS_UART0_PERIPHERAL_IO {PMC_MIO 42 .. 43}
# CONFIG.PS_USB3_PERIPHERAL_ENABLE {1}
# CONFIG.PS_USE_IRQ_0 {1}
# CONFIG.PS_USE_M_AXI_GP0 {1}
# CONFIG.PS_USE_M_AXI_GP2 {0}
# CONFIG.PS_USE_PMCPL_CLK0 {1}
# CONFIG.PS_USE_PS_NOC_CCI {1}
# CONFIG.PS_USE_PS_NOC_RPU_0 {1}
# CONFIG.PS_USE_S_AXI_GP0 {0}
# CONFIG.PS_USE_S_AXI_GP2 {0}
# CONFIG.PS_USE_S_AXI_GP4 {0}
# ] $versal_cips_0
#
# # Create interface connections
# connect_bd_intf_net -intf_net axi_noc_0_CH0_DDR4_0 [get_bd_intf_ports ddr4_dimm1] [get_bd_intf_pins ps_noc/CH0_DDR4_0]
# connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins axi_smc/M00_AXI]
# connect_bd_intf_net -intf_net ddr4_dimm1_sma_clk_1 [get_bd_intf_ports ddr4_dimm1_sma_clk] [get_bd_intf_pins ps_noc/sys_clk0]
# connect_bd_intf_net -intf_net pl_noc_M00_INI [get_bd_intf_pins pl_noc/M00_INI] [get_bd_intf_pins ps_noc/S00_INI]
# connect_bd_intf_net -intf_net ps_noc_M00_AXI [get_bd_intf_pins ai_engine_0/S00_AXI] [get_bd_intf_pins ps_noc/M00_AXI]
# connect_bd_intf_net -intf_net versal_cips_0_FPD_CCI_NOC_0 [get_bd_intf_pins ps_noc/S02_AXI] [get_bd_intf_pins versal_cips_0/FPD_CCI_NOC_0]
# connect_bd_intf_net -intf_net versal_cips_0_FPD_CCI_NOC_1 [get_bd_intf_pins ps_noc/S03_AXI] [get_bd_intf_pins versal_cips_0/FPD_CCI_NOC_1]
# connect_bd_intf_net -intf_net versal_cips_0_FPD_CCI_NOC_2 [get_bd_intf_pins ps_noc/S04_AXI] [get_bd_intf_pins versal_cips_0/FPD_CCI_NOC_2]
# connect_bd_intf_net -intf_net versal_cips_0_FPD_CCI_NOC_3 [get_bd_intf_pins ps_noc/S05_AXI] [get_bd_intf_pins versal_cips_0/FPD_CCI_NOC_3]
# connect_bd_intf_net -intf_net versal_cips_0_M_AXI_FPD [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins versal_cips_0/M_AXI_FPD]
# connect_bd_intf_net -intf_net versal_cips_0_NOC_LPD_AXI_0 [get_bd_intf_pins ps_noc/S01_AXI] [get_bd_intf_pins versal_cips_0/NOC_LPD_AXI_0]
# connect_bd_intf_net -intf_net versal_cips_0_PMC_NOC_AXI_0 [get_bd_intf_pins ps_noc/S00_AXI] [get_bd_intf_pins versal_cips_0/PMC_NOC_AXI_0]
#
# # Create port connections
# connect_bd_net -net ai_engine_0_s00_axi_aclk [get_bd_pins ai_engine_0/s00_axi_aclk] [get_bd_pins ps_noc/aclk6]
# connect_bd_net -net axi_intc_0_irq [get_bd_pins axi_intc_0/irq] [get_bd_pins versal_cips_0/pl_ps_irq0]
# connect_bd_net -net clk_wizard_0_clk_out1 [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins clk_wizard_0/clk_out1] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] [get_bd_pins versal_cips_0/m_axi_fpd_aclk]
# connect_bd_net -net clk_wizard_0_clk_out2 [get_bd_pins clk_wizard_0/clk_out2] [get_bd_pins proc_sys_reset_2/slowest_sync_clk]
# connect_bd_net -net clk_wizard_0_clk_out3 [get_bd_pins clk_wizard_0/clk_out3] [get_bd_pins proc_sys_reset_3/slowest_sync_clk]
# connect_bd_net -net clk_wizard_0_locked [get_bd_pins clk_wizard_0/locked] [get_bd_pins proc_sys_reset_1/dcm_locked] [get_bd_pins proc_sys_reset_2/dcm_locked] [get_bd_pins proc_sys_reset_3/dcm_locked]
# connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn]
# connect_bd_net -net versal_cips_0_fpd_cci_noc_axi0_clk [get_bd_pins ps_noc/aclk2] [get_bd_pins versal_cips_0/fpd_cci_noc_axi0_clk]
# connect_bd_net -net versal_cips_0_fpd_cci_noc_axi1_clk [get_bd_pins ps_noc/aclk3] [get_bd_pins versal_cips_0/fpd_cci_noc_axi1_clk]
# connect_bd_net -net versal_cips_0_fpd_cci_noc_axi2_clk [get_bd_pins ps_noc/aclk4] [get_bd_pins versal_cips_0/fpd_cci_noc_axi2_clk]
# connect_bd_net -net versal_cips_0_fpd_cci_noc_axi3_clk [get_bd_pins ps_noc/aclk5] [get_bd_pins versal_cips_0/fpd_cci_noc_axi3_clk]
# connect_bd_net -net versal_cips_0_lpd_axi_noc_clk [get_bd_pins ps_noc/aclk1] [get_bd_pins versal_cips_0/lpd_axi_noc_clk]
# connect_bd_net -net versal_cips_0_pl0_ref_clk [get_bd_pins clk_wizard_0/clk_in1] [get_bd_pins versal_cips_0/pl0_ref_clk]
# connect_bd_net -net versal_cips_0_pl0_resetn [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins proc_sys_reset_2/ext_reset_in] [get_bd_pins proc_sys_reset_3/ext_reset_in] [get_bd_pins versal_cips_0/pl0_resetn]
# connect_bd_net -net versal_cips_0_pmc_axi_noc_axi0_clk [get_bd_pins ps_noc/aclk0] [get_bd_pins versal_cips_0/pmc_axi_noc_axi0_clk]
#
# # Create address segments
# assign_bd_address -offset 0x020000000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_CCI0] [get_bd_addr_segs ai_engine_0/S00_AXI/AIE_ARRAY_0] -force
# assign_bd_address -offset 0x020000000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_CCI1] [get_bd_addr_segs ai_engine_0/S00_AXI/AIE_ARRAY_0] -force
# assign_bd_address -offset 0x020000000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_CCI2] [get_bd_addr_segs ai_engine_0/S00_AXI/AIE_ARRAY_0] -force
# assign_bd_address -offset 0x020000000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_CCI3] [get_bd_addr_segs ai_engine_0/S00_AXI/AIE_ARRAY_0] -force
# assign_bd_address -offset 0x020000000000 -range 0x000100000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_PMC] [get_bd_addr_segs ai_engine_0/S00_AXI/AIE_ARRAY_0] -force
# assign_bd_address -offset 0xA4000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces versal_cips_0/Data1] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] -force
# assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_CCI0] [get_bd_addr_segs ps_noc/S02_AXI/C0_DDR_LOW0] -force
# assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_CCI1] [get_bd_addr_segs ps_noc/S03_AXI/C0_DDR_LOW0] -force
# assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_CCI2] [get_bd_addr_segs ps_noc/S04_AXI/C0_DDR_LOW0] -force
# assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_CCI3] [get_bd_addr_segs ps_noc/S05_AXI/C0_DDR_LOW0] -force
# assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_PMC] [get_bd_addr_segs ps_noc/S00_AXI/C0_DDR_LOW0] -force
# assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces versal_cips_0/DATA_RPU0] [get_bd_addr_segs ps_noc/S01_AXI/C0_DDR_LOW0] -force
#
#
# # Restore current instance
# current_bd_instance $oldCurInst
#
# # Create PFM attributes
# set_property PFM_NAME {xilinx:vck190_es:VCK190_Custom_Platform:0.0} [get_files [current_bd_design].bd]
# set_property PFM.IRQ {intr {id 0 range 32}} [get_bd_cells /axi_intc_0]
# set_property PFM.AXI_PORT {M01_AXI {memport "M_AXI_GP" sptag "" memory ""} M02_AXI {memport "M_AXI_GP" sptag "" memory ""} M03_AXI {memport "M_AXI_GP" sptag "" memory ""} M04_AXI {memport "M_AXI_GP" sptag "" memory ""} M05_AXI {memport "M_AXI_GP" sptag "" memory ""} M06_AXI {memport "M_AXI_GP" sptag "" memory ""} M07_AXI {memport "M_AXI_GP" sptag "" memory ""} M08_AXI {memport "M_AXI_GP" sptag "" memory ""} M09_AXI {memport "M_AXI_GP" sptag "" memory ""} M10_AXI {memport "M_AXI_GP" sptag "" memory ""} M11_AXI {memport "M_AXI_GP" sptag "" memory ""} M12_AXI {memport "M_AXI_GP" sptag "" memory ""} M13_AXI {memport "M_AXI_GP" sptag "" memory ""} M14_AXI {memport "M_AXI_GP" sptag "" memory ""} M15_AXI {memport "M_AXI_GP" sptag "" memory ""}} [get_bd_cells /axi_smc]
# set_property PFM.CLOCK {clk_out1 {id "0" is_default "false" proc_sys_reset "/proc_sys_reset_1" status "fixed"} clk_out2 {id "1" is_default "true" proc_sys_reset "/proc_sys_reset_2" status "fixed"} clk_out3 {id "2" is_default "false" proc_sys_reset "/proc_sys_reset_3" status "fixed"}} [get_bd_cells /clk_wizard_0]
# set_property PFM.AXI_PORT {S00_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S01_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S02_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S03_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S04_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S05_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S06_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S07_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S08_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S09_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S10_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S11_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S12_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"} S13_AXI {memport "MIG" sptag "MC_NOC0" memory "axi_noc_mc_4int C0_DDR_LOW0"}} [get_bd_cells /pl_noc]
# set_property PFM.AXI_PORT {M00_AXI {memport "NOC_MASTER"}} [get_bd_cells /ps_noc]
#
#
# save_bd_design
# }
# create_root_design ""
WARNING: [IP_Flow 19-2162] IP 'design_1_ai_engine_0_0' is locked:
* IP definition 'AI Engine (1.0)' for IP 'design_1_ai_engine_0_0' (customized with software release 2020.2) has a newer major version in the IP Catalog.
ERROR: [BD 41-542] Parameter cannot be set on a locked block. The block 'ai_engine_0' is locked, because: * IP definition 'AI Engine (1.0)' for IP 'design_1_ai_engine_0_0' (customized with software release 2020.2) has a newer major version in the IP Catalog.
INFO: [Common 17-17] undo 'set_property'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
while executing
"rdi::add_properties -dict {CONFIG.CLK_NAMES {} CONFIG.FIFO_TYPE_MI_AXIS {} CONFIG.FIFO_TYPE_SI_AXIS {} CONFIG.NAME_MI_AXIS {} CONFIG.NAME_SI_AXIS {} C..."
invoked from within
"set_property -dict [ list CONFIG.CLK_NAMES {} CONFIG.FIFO_TYPE_MI_AXIS {} CONFIG.FIFO_TYPE_SI_AXIS {} CONFIG.NAME_MI_AXIS {} CONFIG.NAME_SI_AXIS ..."
(procedure "create_root_design" line 42)
invoked from within
"create_root_design """
(file "system_step1.tcl" line 531)
update_compile_order -fileset sources_1
