FPGA系统性学习笔记连载_Day12【呼吸灯实验】之【另外一种verilog实现】篇

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连载《叁芯智能fpga设计与研发-第12天》【呼吸灯实验】之【另外一种verilog实现】

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这篇文章，记录的呼吸灯的另外一种verilog代码实现，看起来比较直观

一、breath_led.v

代码语言：javascript复制

module breath_led_v1(clk, rst_n, led);
 
  input       clk;
  input       rst_n;
   
  output      led;
 
  reg [6:0] cnt_2us;
  reg [9:0] cnt_2ms;
  reg [9:0] cnt_2s;
   
  always @ (posedge clk, negedge rst_n)
  begin
    if(rst_n == 1'b0)
      cnt_2us <= 7'd0;
    else if(cnt_2us == 7'd99)
      cnt_2us <= 7'd0;
    else
      cnt_2us <= cnt_2us   1'b1;
  end
 
  always @ (posedge clk, negedge rst_n)
  begin
    if(rst_n == 1'b0)
      cnt_2ms <= 10'd0;
    else if(cnt_2us == 99)
      begin
        if(cnt_2ms == 999)
          cnt_2ms <= 10'd0;
        else
          cnt_2ms <= cnt_2ms   1'b1;
      end
    else
      cnt_2ms <= cnt_2ms;
  end
 
  reg change;
   
  always @ (posedge clk, negedge rst_n)
  begin
    if(rst_n == 1'b0)
      begin
        cnt_2s <= 10'd0;
        change <= 1'b0;
      end
    else if(cnt_2us == 99 && cnt_2ms == 999)
      begin
        if(cnt_2s == 999)
          begin
            cnt_2s <= 10'd0;
            change <= 1'b1;
          end
        else
          begin
            cnt_2s <= cnt_2s   1'b1;
            change <= 1'b0;
          end
      end
    else
      begin
        cnt_2s <= cnt_2s;
        change <= 1'b0;
      end
  end
   
  wire led_n;
  reg flag;
   
  assign led_n = (cnt_2ms <= cnt_2s) ? 1'b1 : 1'b0;
   
  always @ (posedge clk, negedge rst_n)
  begin
    if(rst_n == 1'b0)
      flag <= 0;
    else if(change)
      flag <= ~flag;
    else
      flag <= flag;
  end
   
  assign led = (flag) ? led_n : ~led_n;
 
endmodule

二、breath_led_tb.v

代码语言：javascript复制

`timescale 1ns/1ps
 
module breath_led_v1_tb;
 
  reg         clk;
  reg         rst_n;
   
  wire        led;
 
  initial begin
    rst_n = 0;
    clk = 0;
    #105;
    rst_n = 1;
    #1000;
    $stop;
  end
 
  always #10 clk = ~clk;
   
  breath_led_v1 breath_led_v1_inst(
    .clk      (clk),
    .rst_n    (rst_n),
    .led      (led)
  );
 
endmodule